Typical data processor bus system configurations are too slow for use in SoC architecture communications, especially in the case where multiple data streams are simultaneously used. Multiple data streams are typically needed whenever real-time, multimedia, or other high capacity streams are to be transferred or looped through processing units, such as hardware accelerators.
A problem of particular interest relates to the emergence of multimedia applications, and the increased performance demands imposed by third generation (3G) wireless telecommunications systems. This evolution in wireless telecommunications has increased the need for HW acceleration and buffering in mobile phone architectures. However, the integration of the HW processes on a SoC in order to yield a flexible system having a small software overhead is problematic.
Serial buses are the preferred choice for fast off-chip communication, since parallel data buses typically require more connection pins and are prone to skewing errors when used for high speed data transfer. The use of the typical on-chip serial bus for off-chip communications is limited, however, because of the requirement to provide a clocking signal. The clocking signal can be regenerated, which slows down the system, or alternatively asynchronous signaling can be employed.
Failure by a single bus to provide sufficient data transfer speed can quickly become a system bottleneck, making the use of multiple point-to-point connections advantageous in a typical SoC architecture. These multiple point-to-point data streams are, however, complicated to control in a flexible way. The dynamic control of data flow in a SoC architecture is an important consideration when implementing flexible software-driven applications.
Modern Graphical User Interface (GUI) driven multimedia applications generate various and changing data transfer and processing tasks that need to be executed on a hardware platform. The processing of data streams in telecommunications has a great need for hardware acceleration. As was noted above, the emergence of multimedia applications and 3G performance has increased the need for HW acceleration in mobile phone and other architectures.
The flexibility of any type of HW acceleration relies on the operating system being capable of triggering and controlling the HW acceleration, and further having an ability to connect the needed data inputs and data outputs with little overhead. Typically a SW process implementation is used in order to provide flexibility to the system, and HW process implementations are used to facilitate increased speed and reduced power consumption. However, the SW processing becomes a bottleneck when intense SW processing is performed on a data stream, or when SW processing is used to manipulate or transfer large data streams.
As was noted, the integration of the HW processes in a SoC into a flexible system with small software overhead is problematic. High speed fixed connections that can be enabled or disabled, as needed, are known from the prior art. For dynamic connectivity some bus structures have been standardized, such as OMAP™ (Texas Instruments, Inc.). However, these approaches have too low of a transfer capacity, and furthermore do not provide solutions that can integrate multiple simultaneous data streams. The conventional approaches also do not offer a structure for setup and control of the data sources and destinations, nor do they facilitate off-chip process control. Overall, the number of possible data transfer connections such systems allow is low, which limits the flexibility of dynamic data transfer configurations.
The off-chip connections have previously been handled by various serial or parallel communication standards. These conventional approaches, however, are not easily implementable for use as an on-chip data streaming mechanism.